Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/54467
Title: Ultra-low power CMOS circuits
Authors: Tan, Jian An.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Abstract: Technology being ever-changing holds large demand for ultra-low power circuits. Transistors operating in the sub-threshold regions have recently showed large potential for ultra-low power purposes. Having a large variety of circuits/techniques available for sub-threshold operation, many were examined during the course of the project. However, in order to attain ULP consumption, circuit performance was one of the greatest trade-offs incurred when voltage scaling was performed. Besides, transistor sizing also holds a crucial role during circuit design. Investigation of ultra-low power design considerations and techniques were performed via simulations in Cadence software utilizing the Global Foundries 65nm process. This in time led to the development of an application that could prove useful in bidirectional counters.
URI: http://hdl.handle.net/10356/54467
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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SEA2098-121.pdf
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15.46 MBAdobe PDFView/Open
SEA2098-121a.pdf
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Cadence User Manual7.2 MBAdobe PDFView/Open

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