CMOS differential logic circuits for low power design

Abstract

Research will be done on low power consumption circuit of CMOS differential logic. Ever since 1980s, researcher has been looking for alternative circuit design to lower the power consumption of a circuit, with components such as transistor or capacitor getting smaller each year, you can implement million in one small device, power consumption has been a issue ever since, so based on this project, understanding the concept and understanding some of the low power consumption device available and recommend necessary information for the design of a new low power consumption circuit. All the researches information are done based on the some research notes, database from various university lecture notes and data available online.

In this project, software cadence will be use to simulate different circuit from inverter to differential cascode voltage switch logic (DCVSL) and more. Different combinational logic circuit will be use to implement into the logic tree to obtain different result. All Simulation result will be included in this report. The most important points is to understanding the different circuit that will be included in this project as well as obtain testing result in the simulation and obtain the power consumption each circuit.