Low power CMOS parallel prefix adders

Abstract

Addition is the basic operation in many modern electronic applications. As the fastest

adder, parallel prefix adder is of most interest for many circuit designers. For the past

few decades, supply voltage and the size of transistors have been reduced

tremendously. With more and more transistors being integrated on one single chip,

the power issue must be taken care of. Low power adder has been studied for years

and many solutions are proposed. In this paper, a new circuit is designed at transistor

level. The proposed circuit cells adopt transmission gate logic and develop a MUXbased

structure. Simulations are conducted using Cadence. The result shows that the

new adder demonstrates a better performance in terms of power dissipation. It saves

more than 30% energy in all the adders with different word length.