32-bit adders using adiabatic switching for low power IC design

Abstract

This dissertation describes the implementation of 32-bit adders using different

adiabatic logic families. Adiabatic switching is a technique of power reduction where

the energy taken from the power supply is recycled or reused. The adder is the most

commonly used and critical arithmetic operator which determines the throughput of

the processor. It is for this reason that the power reduction is shown in 32-bit adders.

Three adiabatic logic families are used for comparison in this dissertation- Efficient

Charge Recovery Logic (ECRL), Clocked CMOS Adiabatic Logic (CAL) and

Complementary Energy Path Adiabatic Logic (CEPAL). Initially inverter circuits

were implemented using each of these logic styles and compared with vanilla CMOS

in terms of power consumption. Next, I-bit full adder circuits were implemented for

each of the adiabatic logic styles and compared with vanilla CMOS. 32-bit adders

were then implemented and compared to observe the reduction in power

consumption. The adders were also tested to see under what range of voltage and

frequency the operation is consistent. All the circuits were realized using 65nm

CMOS technology using Cadence Virtuoso.

There was a significant reduction in power consumption when adiabatic circuits were

used. ECRL circuit eliminates the need for diodes but the power saving is not

significant compared to the other logic families (44.5% power saving compared to

conventional CMOS). The CEPAL has an edge over the other families because it has

the simplest power clock generator circuitry as only a sinusoidal power clock is

required. However it requires more number of transistors for its implementation. The

power consumption is less than ECRL circuits but more than CAL circuits. When

compared with vanilla CMOS a power saving of 67.8% was observed. The

maximum energy efficiency, 90% saving over conventional CMOS, is observed for

CAL circuits and it can also operate at up to 250MHz at 3V and as low at 1.2V when

operated at 50MHz. The CAL circuit requires an additional square wave clock signal

which acts as an auxiliary clock, thereby increasing the complexity of the power

clock generator.