Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/55131
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dc.contributor.authorLiu, Shijun.
dc.date.accessioned2013-12-19T04:41:29Z
dc.date.available2013-12-19T04:41:29Z
dc.date.copyright2013en_US
dc.date.issued2013
dc.identifier.urihttp://hdl.handle.net/10356/55131
dc.description.abstractA frequency synthesizer is an important component in many communication systems. It plays a role of a well-controlled signal source. Many frequency synthesizers are based on Phase Locked Loop. A signal with large frequency and low phase noise is generated through PLL which is a negative feedback architecture that allows multiplication of crystal frequencies by any variable numbers. So PLL is adapting to generation of steady, low phase noise tunable RF signal for all wireless communication applications.en_US
dc.format.extent66 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleDesign and simulation of a cognitive radio architectureen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
dc.contributor.supervisor2Zheng Yuanjinen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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