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https://hdl.handle.net/10356/55131
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Liu, Shijun. | |
dc.date.accessioned | 2013-12-19T04:41:29Z | |
dc.date.available | 2013-12-19T04:41:29Z | |
dc.date.copyright | 2013 | en_US |
dc.date.issued | 2013 | |
dc.identifier.uri | http://hdl.handle.net/10356/55131 | |
dc.description.abstract | A frequency synthesizer is an important component in many communication systems. It plays a role of a well-controlled signal source. Many frequency synthesizers are based on Phase Locked Loop. A signal with large frequency and low phase noise is generated through PLL which is a negative feedback architecture that allows multiplication of crystal frequencies by any variable numbers. So PLL is adapting to generation of steady, low phase noise tunable RF signal for all wireless communication applications. | en_US |
dc.format.extent | 66 p. | en_US |
dc.language.iso | en | en_US |
dc.rights | Nanyang Technological University | |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering | en_US |
dc.title | Design and simulation of a cognitive radio architecture | en_US |
dc.type | Final Year Project (FYP) | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Bachelor of Engineering | en_US |
dc.contributor.supervisor2 | Zheng Yuanjin | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | restricted | - |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
FYP_Report.pdf Restricted Access | 1.85 MB | Adobe PDF | View/Open |
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