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|Title:||High speed 16-bit multiplier design||Authors:||Zhou, Jiong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2013||Abstract:||Nowadays, in the very-large-scale integration (VLSI) systems, high speed arithmetic circuits are required, such as adders and multipliers, which are extensively and frequently used. This is because in the most of application, such as digital signal processor, the overall performance of the arithmetic circuit will be affected by the multiplier computation speed. In this project, different types of multipliers will be investigated and developed in VHDL. The appropriate parameter values will be determined by behavioral simulations. In the beginning of the project, as limitation of my knowledge, I have to spend a lot of time to obtain the basic knowledge of IC design in Digital Systems using EDA tool and VHDL code techniques. With the basic knowledge, the 16-bit array multiplier was designed and simulated. In the second step of the project, I was adopting the Carry save multiplier idea from last year FYP student’s idea, and I made an improvement which replaced the last row of ripple adder by using Carry Look-Ahead adder and achieve even higher speed multiplier. Meanwhile, different bits (4-bit, 8-bit and 16-bit,) of Carry Look-Ahead adder was designed and simulated successfully. In the last step but not least, another different type of multiplier of 16-bit using modified booth algorithm for partial product generation and summed by Carry Look-Ahead adder was designed and simulated successfully with Critical Path propagation delay of 10.39 ns.||URI:||http://hdl.handle.net/10356/55232||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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