Energy-efficient dedicated DCT processor for wireless image sensor node systems

Abstract

Recently, wireless sensor node systems are widely used in many applications, including healthcare, industry and environment monitorings. Specifically, wireless image sensor nodes are widely used in smart buildings for security monitoring. Energy-efficient DSP processors can be designed and utilized in wireless image sensor nodes to perform image analysis and compression. However, discrete cosine transform (DCT), which is the key component in image compression process, is very time consuming and power hungry. In this study, several fast DCT algorithms are studied and compared. Classical fast DCT algorithms such as the l l-multiplication 8-point DCT algorithm are able to reduce the numbers of addition and multiplication so that the required computation can be minimized, thereby improving on the energy efficiency. The energy efficiency can in fact be further improved using the integer DCT algorithm that has shorter integer arithmetic operations and hence lesser hardware resource, faster computation and lower power consumption. Furthermore, adders and shifters are used to replace multipliers to achieve a higher speed and also lower energy consumption. In this dissertation, a new integer DCT processor is designed with a higher throughput rate as compared to the conventional hardware design. Matlab and RTL simulation had been conducted to verify the functionality of the proposed integer DCT processor design. The analysis and discussion conducted that the proposed energy-efficient integer DCT processor obtained a doubled throughput rate and is hence suitable for use in wireless image sensor node systems in the smart building applications.