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|Title:||A compressor based 16-bit binary-to-residue converter for low power applications||Authors:||Vasuma, Narayana||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2013||Abstract:||With the growing demand for low-power, high-speed electronic devices it has become vital to ensure that all arithmetic modules used in the digital system are power, speed and area-efficient. Arithmetic operations such as addition, multiplication etc. are increasingly using the residue number system representation to increase the speed of computing. This neccessitates the need for binary-to-residue and residue-to-binary converter systems. This project mainly deals with the design of a low-power, high-speed binary-to-residue converter architecture based on compressor blocks. Several techniques exist for the reduction of power consumption in a CMOS circuit.This project focuces on the minimization power consumption through the technique of supply voltage scaling. Since the reduction of supply voltage causes a speed penalty in the system, both power and delay characteristics are studied to obtain the best tradeoff The different logic styles in CMOS circuits vary in their performance characteristics when subjected to voltage over-scaling. Hence, a comparison of the power and delay characteristics of the circuits at ultra-low voltages is presented for the complementary CMOS, dynamic and pass transistor logic styles. At the first stage, the project studies the compressor architectures for the 3:2 compressors, 4:2 compressors and 5:2 compressors. These compressor blocks are realized in the different logic styles using the optimized circuits of XOR and MUX sub-modules. At different over-scaled supply voltage levels, the compressor power consumption and delay characteristics are evaluated. The compressor blocks designed in the first stage are then used in the second stage of the project for the implementation of an efficient modulo (2k-1) binary-to-residue converter system for a l o-bit binary input. A comparative study of the complementary CMOS, dynamic and pass transistor realizations is conducted for the power and delay variation at scaled supply voltage levels to obtain the most efficient logic style for the converter implementation.||URI:||http://hdl.handle.net/10356/55313||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Nov 28, 2020
Updated on Nov 28, 2020
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