Design and implementation of a novel gate-level to behavior-level netlist conversion tool

Abstract

This thesis pertains to the investigation, design and implementation of a novel gate-level to behavior-level netlist conversion tool. The conversion tool is the final stage of the 3-stage circuit function extraction process to explore the functionality of an unknown circuit netlist. The first 2 stages of the process are the microphotograph to transistor-level netlist conversion and transistor-level to gate-level netlist conversion. The gate-level to behavior-level netlist conversion tool consists of three proposed algorithms: a Microcell Identification Algorithm, a Boolean Equation Construction Algorithm and a State Machine Identification Algorithm.