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Title: Optimizing sparse matrix kernels on coprocessors
Authors: Lim, Wee Siong
Keywords: DRNTU::Engineering::Computer science and engineering::Mathematics of computing::Numerical analysis
DRNTU::Engineering::Computer science and engineering::Data::Data structures
DRNTU::Engineering::Mathematics and analysis
Issue Date: 2014
Abstract: Accelerators such as the Graphic Processing Unit (GPU) have increasingly seen use by the science and engineering fields to accelerate applications and computations. However, the GPUs required developers to learn new programming methodologies in order to accelerate such applications. Therefore, in order to solve this issue, Intel released the Xeon Phi coprocessor with the goal of easing such development. In some of these scientific and engineering applications, sparse matrix vector multiplication (SpMV) kernels are sometimes the bottleneck and thus serve as the main focal point for acceleration. In this report, we looked at the performance of SpMV kernels on the coprocessor as well as various optimization methods such as the use of vectorizations, prefetching and the use of auto-tuning to achieve a higher rate of floating-point operations. With our work, we have shown that SpMV kernels could attain much better performance, especially with the use of vectorization, as compared to the basic implementation.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Student Reports (FYP/IA/PA/PI)

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