Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/59200
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dc.contributor.authorLi, Jiaxiang
dc.date.accessioned2014-04-25T04:50:01Z
dc.date.available2014-04-25T04:50:01Z
dc.date.copyright2014en_US
dc.date.issued2014
dc.identifier.urihttp://hdl.handle.net/10356/59200
dc.description.abstractNowadays, the security of data is playing an increasingly important role in the data transfer. The encryption algorithm is the core of the data encryption system and change very fast in the decade. At present, AES (Advanced Encryption Standard) algorithm which is also known as Rijndael algorithm is widely used in the industry. The encryption system can be implemented in hardware and software. Hardware implementation has advantages on cost and can be optimized in aspect of performance, especially in the situation that the data flow is large. In this project, I will use FPGA to implement AES encryption algorithm. This report will focus on how to implement the AES by using FPGA in an efficient way, and by using pipelining, parallel processing and pipeline reconfiguration, we can reduce the risk of power analysis attack. The AES algorithm is implemented by Verilog.en_US
dc.format.extent47 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Computer science and engineeringen_US
dc.titleEfficient FPGA implementation of advanced encryption standarden_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorPramod Kumar Meheren_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.description.degreeBachelor of Engineering (Computer Engineering)en_US
dc.contributor.researchCentre for High Performance Embedded Systemsen_US
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Appears in Collections:SCSE Student Reports (FYP/IA/PA/PI)
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