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|Title:||Efficient FPGA implementation of advanced encryption standard||Authors:||Li, Jiaxiang||Keywords:||DRNTU::Engineering::Computer science and engineering||Issue Date:||2014||Abstract:||Nowadays, the security of data is playing an increasingly important role in the data transfer. The encryption algorithm is the core of the data encryption system and change very fast in the decade. At present, AES (Advanced Encryption Standard) algorithm which is also known as Rijndael algorithm is widely used in the industry. The encryption system can be implemented in hardware and software. Hardware implementation has advantages on cost and can be optimized in aspect of performance, especially in the situation that the data flow is large. In this project, I will use FPGA to implement AES encryption algorithm. This report will focus on how to implement the AES by using FPGA in an efficient way, and by using pipelining, parallel processing and pipeline reconfiguration, we can reduce the risk of power analysis attack. The AES algorithm is implemented by Verilog.||URI:||http://hdl.handle.net/10356/59200||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Student Reports (FYP/IA/PA/PI)|
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