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|Title:||Understanding resource usage and performance in FPGA designs||Authors:||Muhamad Rafiudin Rahim||Keywords:||DRNTU::Engineering::Computer science and engineering::Hardware||Issue Date:||2014||Abstract:||This report concerns FPGAs (Field Programmable Gate Arrays). The basic FPGA blocks, I/O, CLBs (Combinational Logic Blocks), and routing architecture, are discussed to impact a basic understanding of FPGA operation. The Block RAM implementation method for the programming elements of FPGAs is briefly discussed. This project will also highlight the Logic Resource Utilization of each FPGA Family in Xilinx and in Altera. We will discuss the highlights of our report further into the paper. But before doing all the highlights, we will first understand the concepts of FPGA, fundamentals of it, and also the different ways each companies built their FPGAs. We will focus on making a complicated FPGA to a simple primitive logic resource. For example, Altera uses Adaptive Logic Module to implement flexible Logic Element while Xilinx uses Combinational Logic Block to implement logic functions. The purpose for each of this is to compare using a metric that can be use all types of FPGA regardless of where they were manufactured from.||URI:||http://hdl.handle.net/10356/59256||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Student Reports (FYP/IA/PA/PI)|
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