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dc.contributor.authorKlyne, Raymond
dc.description.abstractMulti-core processors are the way to go in today’s computing applications, and provide several orders of magnitude higher processing speed and power than their single core counterparts. But new advancements bring new problems. Multi-core processors have now become increasingly unpredictable in their execution patterns when they start to use shared resources. These shared resources include shared cache, the controllers of the shared cache, main memory (DDR), the controllers of DDR, and finally the bus that connects them all together. When multiple cores try to access memory at the same time, some cores will have to wait for others because there are only a limited number of cache and memory controllers to serve the requests of the cores. Also, when cores start overwriting each other’s data in cache due to the limited cache space, a certain piece of data that is soon to be needed by another core would no longer be there, The core that needs this just-evicted data will then have to wait a long time for the memory controller to retrieve it from main memory, thereby slowing down its processes. Simple experiments which simulated such contention behavior showed that the performance of the program suffers greatly as the number of cores running in parallel is increased.en_US
dc.format.extent25 p.en_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Computer science and engineeringen_US
dc.titleProfiling a multicore : freescale P4080en_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.description.degreeBachelor of Engineering (Computer Engineering)en_US
dc.contributor.researchCentre for High Performance Embedded Systemsen_US
dc.contributor.supervisor2Arvind Easwaranen_US
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Appears in Collections:SCSE Student Reports (FYP/IA/PA/PI)
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