dc.contributor.authorChen, Xiangchen
dc.date.accessioned2014-05-07T06:32:34Z
dc.date.accessioned2017-07-23T08:35:13Z
dc.date.available2014-05-07T06:32:34Z
dc.date.available2017-07-23T08:35:13Z
dc.date.copyright2014en_US
dc.date.issued2014
dc.identifier.citationChen, X. (2014). Gate-all-around silicon nanowire FET modeling. Master’s thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/59526
dc.description.abstractAs a further extension of the multi-gate MOSFET, the gate-all-around (GAA) silicon nanowire FET is the most promising nanostructure design for next generation semiconductor device. Recent research work demonstrates the excellent device performance of GAA silicon nanowire FET, especially the gate controllability and short channel effect immunity. In this work, the device modeling of GAA silicon nanowire FET is presented. The modeling work is performed in TCAD environment, and several essential modeling topics are discussed. The process modeling and device characterization modeling are first investigated since these are the fundamental part of this project. The carrier transport selection, device self-heating effect and process induced stress effect are discussed based on the modeling results. The performance advantages of GAA silicon nanowire FET is then evaluated by conducting a comparison study between the GAA FET and FinFET. The electrostatic discharge (ESD) modeling on GAA silicon nanowire FET is then discussed. From a contrast study to verify the simulation model with reported experiment work, the accuracy of proposed modeling is confirmed. Based on the ESD modeling, further device degradation characterization is performed and the degradation mechanism is explained. Under the ESD stress, the GAA silicon nanowire FET is found to degrade due to the hot carrier induced interface state generation. In the condition of severe stress, the device melts catastrophically and results in hard breakdown. Both degradation phenomenons are supported by modeling result and experiment conclusion. The random dopant fluctuation (RDF) effect is also discussed on the GAA silicon nanowire FET in this work. The RDF is a major process variation issue due to discrete dopant atom placement. The statistical simulation methodology is integrated with device simulation to characterize the RDF effect. From the extracted characterization result, the GAA silicon nanowire FET shows good RDF robustness which benefits from the intrinsic nanowire doping. A semi-analytical model is also introduced to study the RDF variation of GAA silicon nanowire FET. Last but not least, the junctionless GAA silicon nanowire FET is also introduced. As an alternative design of GAA silicon nanowire FET, the junctionless device shows excellent electrical performance as its inversion mode counterpart. However, from the device characterization result and semi-analytical analysis, the junctionless device also shows more severe performance variation problem due to RDF which could limit its further practical usage.en_US
dc.format.extent149 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Nanoelectronicsen_US
dc.titleGate-all-around silicon nanowire FET modelingen_US
dc.typeThesis
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorTan Cher Mingen_US
dc.description.degreeMASTER OF ENGINEERING (EEE)en_US


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