High PSRR linear low dropout regulator (LDO)

Abstract

In many on-chip systems, low dropout regulators (LDO) are used to provide a clean power supply to various blocks, while taking in noisy supply from more efficient DC-DC converters. Sensitive analog blocks such as analog-to-digital converters (ADCs) require a very clean supply voltage to perform optimally, making it imperative that the LDOs supplying these sensitive blocks have a very good power supply ripple rejection (PSRR). This work introduces a method to reduce supply ripple at the output of the LDO, all while working within the constraints of low power and no external output capacitor.