Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/60378
Title: Logic-compatible embedded dynamic random access memory design
Authors: Wang, Yue
Keywords: DRNTU::Engineering
Issue Date: 2014
Abstract: Nowadays, EDRAMs become a new direction in the research society since it has higher density. However, poor data retention time due to small storage capacitor and various leakage paths has become the main issue, which results in high power consumption and poor read performance. In this FYP, the author develops two circuit techniques to improve the data retention time by analyzing the leakage currents of different EDRAM cell configurations. Firstly, the author mainly discusses the effects of different design parameters on the data retention time. Basically, four parameters are talked about, which include gate biasing voltage of write transistor; body biasing voltage of write transistor; channel length of write/storage transistor and channel width of write/storage transistor. To optimize data retention time, a proposed procedure can be used. As a result, data retention time for Conv_P cell can be enhanced by more than 2.5 times by using 65nm process. Secondly, in EDRAM cell design, PMOS transistor is more often used as write transistor since it has lower gate leakage compared with that of NMOS. To further improve its data retention time, different Vth transistor combinations are mainly concerned. Three configurations include Conv_P, Conv_N and C2T_PN cells are used to test. As a result, cells with HVth write transistor has much longer data retention time compared with LVth write transistor.
URI: http://hdl.handle.net/10356/60378
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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