Please use this identifier to cite or link to this item:
Title: Ultra low quiescent current slew rate enhanced OCL-LDO
Authors: Chua, Jocelyn Shin Hun
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2014
Abstract: A high slew-rate amplifier is proposed in the Ultra-Low Quiescent Current Slew-Rate Enhanced OCL-LDO regulator design with improved transient response, using push-pull output to enhance driving capability that only requires ultra-low quiescent current (IQ ~1μA ). Using the tail-current in conventional amplifier design eliminates the trade-off between small IQ and high slew-rate. Minimum power loss of OCL-LDO regulator without transient-response degradation is implemented by small dropout voltage VDO with large-size pass transistor and ultra-low IQ. With the proposed design, stability of OCL-LDO regulators has gradually improved without using any on-chip and off-chip compensation capacitors. This is beneficial to technologies which require high-area efficiency.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
FYP Final Report.pdf
  Restricted Access
1.84 MBAdobe PDFView/Open

Page view(s) 50

checked on Oct 21, 2020

Download(s) 50

checked on Oct 21, 2020

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.