Please use this identifier to cite or link to this item:
Title: Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system
Authors: Tsui, Yun Kan
Keywords: DRNTU::Engineering
Issue Date: 2014
Abstract: This report targeted to explore the characteristics of different types of asynchronous logic quasi-delay-insensitive circuit design. High performance electronic circuit is the main design goal for current technology. However, the performance of traditional synchronous logic circuit is often limited by the global clock signal. Asynchronous logic should be the future direction of logic design that have the potential to overcome this issue. In this project, five types of asynchronous design technique, which included Static/Dynamic/Pass Logic Transistor-level Implementation, Pre-Charged Half-Buffer and Weak-Conditioned Half- Buffer and four key parameters, which included Delay, Power consumption, Energy consumption and Number of transistor used were experimented. The results of this project showed each type of design technique has its unique characteristic. A complete comparison table is included in the appendix to provide a clear comparison of the results obtained in this project.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
Final Year Project Report (DONE).pdf
  Restricted Access
2.37 MBAdobe PDFView/Open

Page view(s) 50

checked on Oct 26, 2020

Download(s) 50

checked on Oct 26, 2020

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.