Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/60817
Title: 16-bit high speed multiplier design
Authors: Yeo, Melvin Shung Shii
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2014
Abstract: Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissipation of the multiplier, Wallace Tree Algorithm and Modified Booth Algorithm has been proposed to perform the partial product additions. Also Ripple Carry Adder and Carry Lookahead Adder have been proposed for the final addition of the partial products for any improvement.
URI: http://hdl.handle.net/10356/60817
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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