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dc.contributor.authorYang, Yu-
dc.description.abstractThis final year project aims to design an audio single-ended filterless Class D amplifier used in earpiece. A 3-level PWM signal is to be produced at the load for this purpose. Due to the fact that both left and right channels of earpiece share the common ground, the single-ended structure is required for the purpose of this study. During the design process, a digital control block is successfully designed to transform the 2-state PWM signal into a 3-state PWM signal. Meanwhile, a digital buffer is designed to achieve a high forward loop gain in order to attenuate the noise. A hysteresis comparator is designed to generate the control signal. The single-ended filterless Class D amplifier is designed with high fidelity. Simulations are carried out in Cadence Spectre with CSM018 process. This design is verified to have achieved high PSRR (>120dB at 1 kHz) and low THD (<0.006% at 1 kHz and modulation index of 0.6). The elimination of the bulky LC low pass filter endows this design with advantages of lower cost and smaller sizes. At the meantime, the single-ended structure optimizes the design configuration by significantly cutting down hardware overhead compared with differential configuration. In a nutshell, the proposed design meets all the objectives of this final year project and provides an insight to the design of Class D amplifiers. Class D amplifiers can feature with high linearity which is comparable to its linear counterparts as well as high efficiency.en_US
dc.format.extent57 p.en_US
dc.rightsNanyang Technological University-
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleClass D amplifiersen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorChang Joseph Sylvesteren_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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