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|Title:||Nanoscale characterization of advanced high-κ gate dielectric stacks via scanning tunneling microscopy||Authors:||Yew, Kwang Sing||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Microelectronics||Issue Date:||2014||Source:||Yew, K. S. (2014). Nanoscale characterization of advanced high-κ gate dielectric stacks via scanning tunneling microscopy. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Gate leakage is the major driving force for the integration of high-κ dielectric in the silicon-based CMOS technology at sub-45 nm nodes. By virtue of the higher dielectric constant value, high-κ metal oxide provides a physically thicker insulator in suppressing the gate leakage while achieving the gate capacitance identical to that of an ultrathin SiO2 insulator. However, the performance and reliability of high-κ dielectric are severely compromised by an inherently high density of as-grown defects and the phase change induced by the high-thermal-budget front-end process. Reliability studies of the high-κ degradation mechanism result in inconsistent interpretations due to unresolved microscopic information. We address these issues by analyzing the microscopic data of the local defects extracted using ultra-high vacuum scanning tunneling microscopy (UHV-STM). We show directly that the degradation and BD of the SiOx IL of polycrystalline HfO2/SiOx gate stack depends ultimately on the state of the thicker high-κ. A high degree of non-uniformity in the distribution of traps density is observed for a given high-κ area, with the leakage sites tend to center near GB. We demonstrate that the multistep deposition cum annealing method retains the amorphous-like structure of the high-κ film by effectively suppressing the formation of large grains following a high temperature (1000ºC) anneal. Localized electrical stress via STM probe reveals (i) a significantly narrower spread in the leakage current values, (ii) strong retardation of the gate stack BD process. The improvements are ascribed to the partially suppressed formation of the GBs in thin films constituting the multi-step dielectric. We reveal that the substantial improvement seen in the multistep-deposited cum UVO-annealed TiN/HfZrO/SiOx gate stack, relative to the rapid thermal-annealed (RTA) sample, is predominantly contributed by the suppressed crystallization of the high-κ layer rather than the UVO annealing effect. We show that by (i) extending the UVO anneal time after each deposition step, or (ii) increasing the number of deposition steps, a further improvement can be achieved. A 25-Å HfO2 film, deposited directly onto the HF-last Si surface via multistep deposition cum two-step annealing (comprising a room-temperature UVO anneal and a subsequent 420ºC RTA) method is shown to exhibit (i) a significantly reduced gate current density, (ii) a longer time-to-breakdown (TBD), and (iii) a lower positive oxide trapped charge generation, as compared with the as-deposited, UVO-only and RTA-only gate stacks. We show that the bimodal Weibull distribution, obtained from the area-scaling of the high-κ/metal gate device BD statistics, is a combined effect: (i) the steep Weibull slope of the lower percentile, arising from large-area devices, is related to BD at GBs, and (ii) the shallow Weibull slope of the upper percentile, arising from small-area devices, is mostly related to grain BDs.The novelty of this study lies in the application of STM in identifying the GB and grain in a polycrystalline high-κ film, thereby allowing us to probe the local electronic properties and BD strength of GB and grain individually.||URI:||https://hdl.handle.net/10356/61038||DOI:||10.32657/10356/61038||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Jul 30, 2021
Updated on Jul 30, 2021
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