Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/61153
Title: Development of an advanced nano-satellite VELOX-I-study of high speed motion detection CMOS image sensor design
Authors: Huang, Jing
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2014
Abstract: This final year project is one part of the VELOX-I satellite series projects. After launching Singapore’s first two home developed satellites, VELOX-I nano-satellite has been scheduled to launch next. Image sensor is a part of the subsystems as one of the main functions of the satellite is to take pictures of the aerospace. In a conventional image sensor, the readout circuit is controlled by a clock and sequentially reads out the pixel value regardless of the pixels’ activeness. The conventional readout circuit is short of speed since most pixels are inactive in aerospace. This project is to speed up the signal processing a CMOS image sensor with address event represented (AER) - based readout circuit was developed. The main function of the readout circuit is to read only active pixel values and skip the inactive ones. With the new developed readout circuitry, the number of clock cycles consumed for processing each row signal equals to the number of active pixels. During the design, simulations were conducted to test the function and accuracy of the circuit. Finally a 128-to-1 arbitration tree was designed and the layout design for each arbiter tree unit was 10umx10um in size. The column buffer was also designed as an important part in this project. The main function of the column buffer is to communicate the pixel signals with the readout circuit. After the design of each block, a simulation on the integration of each block including a 16x4 pixel array, which were designed based on 4T-APS, was conducted and the processing time had been reduced to a great extent. The image sensor with arbitration based readout circuitry design was realized. The schematic of an image sensor with 4 row 16 column pixel array was simulated and the layout of the simulated image sensor was also built.
URI: http://hdl.handle.net/10356/61153
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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