Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/61286
Title: Hardware Trojan detection based on the side-channel signal analysis
Authors: Lee, Liang Yuan
Keywords: DRNTU::Engineering
Issue Date: 2014
Abstract: With the globalization of integrated circuit design and fabrication process, the main concerned issue is that a malicious logic component which can be intentionally embedded into circuit during the manufacturing and fabrication processes. The malicious logic component can be referred to as hardware Trojan. It will leak the users’ confidential information out to the adversary, reduce the overall system performance and even worse situation will be a fatal damage on the system. These vulnerabilities would cause serious impact on various ways like military system, hardware security, and so on. Over the year, side channel analysis which is one of most popular method in hardware Trojan detection has been used to detect the presence of hardware Trojan due to its advantages such as non-invasiveness, simplicity and low cost. This work presents a proposed novel technology how to detect hardware Trojan is based on power side channel analysis. This method is about designing a current sensing circuit to generate a current waveform on the power grid respect to timing pulse to check whether the circuit is infected by hardware Trojan or uninfected by hardware Trojan. It also will increase the sensitivity of hardware Trojan detection by combining the current waveform with path sensitization abnormalities into a single side channel signal that result can be easily obtained by using this current sensing circuit design. The main advantage of this current sensing circuit design is that the impact of process variation can be reduced. The different current waveforms between the infected circuit and original circuit can be observed through the current sensing circuit. The result will be a significant difference regardless of considering the process variation. This proposed sensing circuit has been executed by using the 65 nanometer of Chartered Semiconductor Manufacturing (CSM 65nm). The ISCAS-85 test benchmark with high level gate design circuits are used in this experiment by software of CADENCE System Design, Virtuoso.
URI: http://hdl.handle.net/10356/61286
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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