Low complexity and low power FIR filter design
Date of Issue2014
School of Electrical and Electronic Engineering
Centre for Integrated Circuits and Systems
With the advent of information era, the use of digital devices such as hand phones, digital cameras and hearing aids becomes more and more pervasive. Digital finite impulse response (FIR) filters are essential components in these devices. In order to save the cost and increase battery life for these portable digital products, in the past decades, many efforts have been dedicated for the design and implementation of low hardware cost and low power FIR filters. Among many others, one of the most successful techniques for such filter design and implementation is known as multiplierless FIR filters, i.e., the general coefficient multipliers can be replaced with adders and shifts in this technique. In multiplierless FIR filters, the hardware cost is proportional to the number of adders since the shift can be hard-wired and thus considered cost-free. Reducing the number of adders therefore can reduce the hardware cost directly and it is also generally believed that it can reduce the power consumption indirectly. Existing algorithms thus mainly aim to minimize the adder cost. The limitation of existing algorithms lies in two aspects. First, the computational complexity to achieve the minimum number of adders is too high to be used in the design of long filters, and second, the number of adder criterion is too coarse and inaccurate for the minimization of power consumption. Therefore, the research in this thesis deals with the issues of designing multiplierless FIR filters to minimize the hardware cost and power consumption. The research is conducted in the following two aspects.First, several optimization techniques with reduced algorithm complexity are proposed and thus are capable of designing long multiplierless FIR filters. The proposed optimization techniques are improved genetic algorithm and polynomial time tree search algorithm. Design results show that the proposed techniques can efficiently generate the FIR filters with low hardware cost. In addition, in order to further reduce the hardware cost, an algorithm is proposed for the design of FIR filters in multiple-stage cascade form with discrete coefficients.Second, besides the number of adders, more criteria are considered in the design of FIR filters with minimum power consumption, including the logic depth and operating frequency. In this thesis, an algorithm trading off the minimum number of adders and the minimal logic depth is first proposed. Besides that, a power model that more accurately describes the power consumption is developed and used for the design of FIR filters. The power model also takes both the dynamic power and static power into consideration. Thus, for the first time, the designed filters are frequency aware, i.e., for the same filter specifications, the proposed algorithm may generate different designs for filters operating at different frequencies, and the designed filters consume the minimum power for the respective frequencies.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits