Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/61400
Title: Low power CMOS circuits
Authors: Teo, Kok Chin
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2014
Abstract: Basic building block of CMOS integrated circuit like inverter, NAND, Latch and Full Adder will be simulated under low voltage condition using the Cadence software. This is an attempt to study the operations of these circuits when voltage is lowered to reduce the power consumption. Results will then be used to observe the impact of the voltage reduction on speed, data distortion and power consumption. Limit on the operating voltage at the testing frequency and the quality of the waveforms when the frequency is reduced can also be observed. Testing is also conducted for different design of Full Adders to understand how different design may also impact the performance at low operating voltage. This will also demonstrate how utilizing different design may also be a good method to reduce power consumption.
URI: http://hdl.handle.net/10356/61400
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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