Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/61424
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dc.contributor.authorWong, Zhen Lin
dc.date.accessioned2014-06-10T04:04:37Z
dc.date.available2014-06-10T04:04:37Z
dc.date.copyright2014en_US
dc.date.issued2014
dc.identifier.urihttp://hdl.handle.net/10356/61424
dc.description.abstractA CMOS fully differential programmable gain amplifier (PGA) has been designed for RF receiver. It uses binary weighted switching techniques to allow switching of gain a various steps. This configurations consist of four differential pair input which reduces common noise and four active load which will help in getting the desired gain with the formula of gmRL. These four stages of gain will form the 24 (16 steps) gain steps while the most significant bit will deduce if it is a positive or negative gain. Thus, completing a 5 bits (32 steps) programmable gain amplifier. It also includes a common mode feedback to help obtain desired DC output at a particular voltage depending on the input common mode requirement of the next stage. The gain of PGA varies from -24dB to 24dB with respect to the input reference. It also has an operating bandwidth greater than 14MHz. It consumes about 1.1mW total power and has 1dB compression point of -2.3dBm. IIP3 was also found to be around 2.4dBm. All results are achieved with differential pair and load in saturation region instead of sub-threshold region which provide high level of gain. This circuit is designed base GlobalFoundries 65nm CMOS technology.en_US
dc.format.extent47 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineeringen_US
dc.titleProgrammable gain amplifieren_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorBoon, Chirn Chyeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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