Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/61470
Title: Protecting FPGA design with elliptic curve cryptography
Authors: Wei, Wei
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2014
Abstract: Designs implemented on SRAM-based FPGA chips are vulnerable to attacks. When the bitstream containing the design information is transmitted from the external NVM (Non-Volatile Memory) to the chip for configuration of the desired functionality, an attacker can eavesdrop on the bus in between, capture the bitstream, and hence steal the design if it is not protected. This problem can be solved by encrypting the bitstream using Elliptic Curve Cryptography (ECC). In this project, an efficient ECC-based cryptosystem on FPGA is designed and implemented. The cryptosystem is based on NIST-recommended B-163 elliptic curve, which securely protects the bitstream against most of the perceivable attacks. With elaborative optimization of the point multiplication operation, the key operation of ECC, the occupied FPGA logic resources of the implemented cryptosystem is minimized while a good performance is maintained. Besides verifying the functionality of the designed cryptosystem through simulation, this project implements the cryptosystem on Xilinx FPGA chips, XC3S700a and performs on-board test with a developed assembly program that runs on Xilinx PicoBlaze Microcontroller. Both the successful encryption and decryption operations of the cryptosystem are confirmed. With the minimal resource consumption, the designed ECC based cryptosystem can be used to protect the bitstreams running on almost all kinds of SRAM-based FPGAs. In terms of performancespeed, the throughput of the designed FPGA based cryptosystem is 1 to 2 magnitudes better than the same system written in C++. is over 4 times better than the design in [3] which implements the same encryption and decryption algorithms. This report discusses the complete FPGA design process, including architectural design, scheduling, Verilog coding, simulation and on-board verification.
URI: http://hdl.handle.net/10356/61470
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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