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|Title:||Controller design for switched-mode system||Authors:||Mai, Quoc An||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2014||Abstract:||The trend of pushing signal processing into the digital domain has penetrated into the analog-dominated power management ICs such as switched-mode DC-DC converters. While digital control for switched-mode DC-DC converter at high-power, low switching frequency domain has been pervasive, it applications in low power, high-switching frequency has been limited due to the complex hardware and high power consumption. The focus of this project is to design a digital controller for switched-mode DC-DC converter operating at high frequency and low power levels that has simple hardware architecture and low power consumption. The design target of the DC-DC Converter is to generate a output voltage of 1.5V from the input voltage 3V and a high switching frequency of 5MHz. This report describes the design of a high frequency digital DC-DC buck converter that uses voltage mode control with digital feedback. The DC-DC converter consists of a power switching stage, a low pass filter stage and a digital feedback architecture comprising an Analog to Digital (A/D) converter, a digital compensator and a digital pulse width modulator (the key building blocks behind digital control). An automated algorithm that help designers design the discrete compensator based on the design specifications has been developed and implemented in Matlab. Two different Simulink models of the proposed digital DC-DC Buck Converter has been create to verify the transient response performance of the converter with the compensators designed using the above algorithm. Finally, the discrete compensator has been designed and simulated using Verilog HDL. The designed Verilog use only 88 Flip Flops, 108 look-up-table, 60 slices, which accounted for less than 10% the total components of the FPGA Board Spartan-3. It also has a low power consumption of only 42mW, which satisfied the design requirement.||URI:||http://hdl.handle.net/10356/61516||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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