Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/61597
Title: Development of carbon nanotubes for interconnects and nano-packaging applications
Authors: Yap, Ray Chin Chong
Keywords: DRNTU::Engineering
Issue Date: 2014
Source: Yap, R. C. C. (2014). Development of carbon nanotubes for interconnects and nano-packaging applications. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: As the scaling in CMOS technology is nearing its limits, the new scaling trend emphasize on making chips smaller, with higher performance and more functionality. This is putting a huge demand on the backend packaging modules, and the industries are now looking at the various challenges faced at the packaging level. Furthermore, with the blooming demand of mobile, wireless and satellite communication, there is a particular strong interest to look for electrical interconnects for tetra hertz applications. Even though, new materials with higher performance, such as carbon nanotubes (CNTs) are being identify as one of the emerging solutions, there are still processing challenges which must be addressed before these emerging materials can become a reality. In this thesis, a systematical approach is taken to look at the different challenges of integrating CNTs as off-chip interconnects. The key challenges include, but are not limited to (1) growth of CNTs of different properties, (2) integrating of CNTs onto metal electrode, (3) joining methodology between the chip and carrier, as well as to (4) grow high aspect ratio CNTs bundles for through silicon vias (TSVs). The significant outcome of this thesis is to demonstrate the growth of CNTs on metal, to control properties of graphene, to present the first CNT flip chip structure for high frequency application, as well as to propose a new bonding technique which enables growth of CNTs in high aspect ratio TSV. First, the synthesis of CNTs using two different approaches; plasma enhanced chemical vapor deposition (PECVD) and thermal chemical vapor deposition (TCVD), and its growth parameters are being studied. The growth techniques are then applied to assist CNTs growth directly onto metal lines. It is found that a barrier layer between catalyst film and metal is necessary to have vertically aligned CNTs bundles on common metals such as Au and Cu. Different barrier layers are being investigated and the effects of barrier layers on CNTs growth are being established. Our results show that bilayer Titanium - Titanium nitride barrier layer and aluminum - aluminum oxide were found to be the two best solutions for barrier layers with good conductivities. Apart from the synthesis of CNTs, the joining methodology of CNTs to metallization is also very important to reduce the contact resistances. A novel joining methodology which involves CNT to CNT “bonding” (CNT interconnections bumps) is being realized. It has been demonstrated that this technology can be applied to CNT bumps with 20 μm diameter, which is in-line with the roadmap of the semiconductor industries. Subsequently, this joining approach is transferred to a flip chip test structure. The performance of the CNT flip chip structures are being evaluated experimentally and by modeling. Both results show that the transmission through CNT bumps up to 40 GHz is possible. The RF characteristics of the CNT interconnections bumps are found to match that of Au metallization up to 40 GHz. This is the first CNT flip chip test structure ever reported in the literatures. Beside flip chip bumps, TSVs is also one of the keys towards 3D packaging integration. As the key challenge of CNT TSVs is the elimination of CNTs growth on sidewalls, a novel approach to bond catalyst wafers to TSV holding substrate is proposed. CNTs are shown to grow successfully through the high aspect ratio TSVs using this new modified fabrication approach. Finally, in order to realize an all carbon integration scheme for electronics packaging, a process flow involving CNT-Graphene TSV has been proposed. The control modulation of graphing using a CMOS compatible process has also been demonstrated.
URI: http://hdl.handle.net/10356/61597
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:CEE Theses

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