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|Title:||Design of an ultra low-power CMOS analog-to-digital converter for biomedical applications||Authors:||Yuan, Chao||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2014||Source:||Yuan, C. (2014). Design of an ultra low-power CMOS analog-to-digital converter for biomedical applications. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The ever increasing healthcare cost has become a burden for modern society. Recently, a lot of research activities have been carried out in search of innovative and low-cost solutions for the healthcare industry. Benefited from advanced submicron CMOS technologies, which allow a high level of integration and reduction of cost, many miniaturized biomedical devices were developed for different applications. The biopotential signals, such as Electroencephalogram (EEG), Electrocardiogram (ECG) and Electromyogram (EMG), were recorded and studied with customized CMOS devices. These low-cost portable CMOS based biomedical devices operating at low supply voltage, which can be battery-powered, will be able to replace the conventional lab-based bulky diagnosis or monitoring systems in the near future. In a typical biomedical acquisition and monitoring system, the biomedical signals, which could be in the form of pressure, PH value, nerve stimulus, or electrical potentials, are usually sensed by single or multi-channel sensors, amplified by a low-pass or bandpass amplifier, digitized by an ADC and then transmitted to the data processing unit. One of the most critical and power consuming components in such system is the ADC. Therefore, minimizing the power consumption is a crucial design target for ADC in biomedical applications. The Successive Approximation Register (SAR) ADC exhibits significant advantages compared to other ADC architectures such as pipelining and Delta-Sigma, in terms of power consumption and area. Two distinct types of SAR ADCs, namely the unit-capacitor array SAR ADC and binary-weighted capacitor SAR ADC, were studied and analyzed in this report. The unit-capacitor array ADC has theoretically the lowest DAC power consumption. However, the digital circuit overhead is large. Two binary-weighted capacitor SAR ADCs were designed and implemented. A novel tri-level switching algorithm that allows 97% Digital-to-Analog Converter (DAC) power reduction and 75% area savings is also proposed. Customized digital logic circuit offers variable sampling rates for different applications and also further reduce ADC power up to 50%||URI:||https://hdl.handle.net/10356/61732||DOI:||10.32657/10356/61732||Schools:||School of Electrical and Electronic Engineering||Research Centres:||Centre for Integrated Circuits and Systems||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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Updated on Sep 27, 2023
Updated on Sep 27, 2023
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