Through-silicon-via (TSV) design, fabrication and characterization for 3D IC applications
Date of Issue2014
School of Electrical and Electronic Engineering
Institute of Microelectronics
Three-dimensional (3D) integration is identified as a key and promising path, not only to facilitate the continuation of the conventional scaling, but also to enable the “More-than- Moore” heterogeneous integration of a vast different functionalities into a system in a single chip form. By using 3D integration in integrated circuits, potential benefit gains such as density, performance, heterogeneous integration, and lower cost can be achieved. Through- Silicon-Via (TSV) technology can provide shorter interconnection lengths; this translates to a lower inductance and conductance loss. In addition, TSV can also be designed and embedded in a 3D integrated circuit (IC) stack to assist in heat removal, which is a critical challenge facing 3D IC. Moreover, thermo-mechanical stress due to the mismatch of the coefficient of thermal expansion (CTE) between Si and TSV Cu core has critical effects on the active device performances in the vicinity of the TSV. In this thesis, fabrication processes and results of TSVs with 5 μm of diameter and aspect ratio of 1:2 to 1:3 are discussed. The results show that super-conformal filling TSVs with plasma enhanced tetraethylorthosilicate (PETEOS) oxide, black diamond low-ĸ, bi-layer of Al2O3 and PETEOS oxide and bi-layer of Al2O3 and low-ĸ liners are successfully fabricated. In our electrical C-V measurements, we show that through careful process tuning, we are able to shift the C-V curve to achieve accumulation capacitance within the operating voltage of interests (~0-5 V). This was due to the PETEOS oxide liner deposition process which introduces beneficial negative fixed charges, and is estimated to have a density of charge of ~ -8.43 × 1011 cm-2 corresponding to a shift of +7.5 V in the positive flat-band voltage (VFB). In comparison to the inversion capacitance which changes rapidly with substrate dopant concentration, small signal frequency and temperature fluctuation, the accumulation capacitance is stable and independent on the substrate temperature for better prediction and control of signal transmission in TSV in the presence of non-uniform hotspot heating. At the same time, in order to further reduce the accumulation capacitance, TSVs with black diamond low-ĸ material as the liner were also successfully fabricated and the C-V results show that the capacitance is reduced by ~28% compared with the TSVs with conventional PETEOS oxide liner. In addition, novel material selection of a thin Al2O3 (~ 10 nm) has been integrated between the Si substrate and the dielectric liner successfully by utilizing atomic layer deposition (ALD) process. The Al2O3-induced negative fixed charge, which has the density on the order of ~ -7.44 × 1011 cm-2, could be effectively utilized to shift the C-V curve so that stable accumulation capacitance was obtained. The corresponding flat- band voltage (VFB) shift is +7.1 V. Electrical I-V measurements are carried out to monitor the leakage current of the dielectric liners from the TSV Cu core to the Si substrate. The results show that no catastrophic breakdown within the desired operating voltage range for all the liners, but the low-ĸ liner was expected to introduce higher leakage current than the oxide liner due to its porosity. After annealing in forming gas (H2/N2) at 350oC for 30 min, the leakage current density of the low-ĸ liner reduced from ~6.8 × 10-6 A/cm2 to a comparable level of oxide liner which is ~1.2 × 10-6 A/cm2. In order to study the thermal properties of TSV, a doped polysilicon line as a heat generator surrounded by rows of TSVs of different dimensions and densities were fabricated. It was found that the use of appropriate TSV arrays which surround and are placed beneath a temperature sensor have an effective cooling capability of as much as ~40°C. Finite element analysis (FEA) modelling and high resolution micro-Raman analysis are carried out to monitor and compare the thermo-mechanical stress exerted on the Si substrate of TSV structures with different TSV diameters and liners. Results show that scaling down the TSV size could improve the stress, since the Cu core volume is decreased. Also it is shown that the low-ĸ liner, due to its smaller elastic modulus (~4.2 GPa), acts as a compliant layer to cushion the Cu-TSV stress on the Si compared with PETEOS oxide (~75 GPa). This relaxes the keep-out-zone (KOZ) requirement. KOZ is imposed around a TSV where no other devices can be placed within a KOZ to minimize the performance degradation due to the stress induced by the TSVs. The higher the KOZ is, the lower the silicon area utilization is.
DRNTU::Engineering::Electrical and electronic engineering::Semiconductors