Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/61794
Title: Ultra low-power asynchronous-logic design for high variation-space and wide operation-space applications
Authors: Lin, Tong
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2014
Source: Lin, T. (2014). Ultra low-power asynchronous-logic design for high variation-space and wide operation-space applications. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: This thesis pertains to the design of low-power/ultra low-power high variation-space and wide operation-space digital electronics for portable/mobile applications. High variation-space and wide operation-space respectively refer to error-free operation despite high variations in the prevailing conditions (including Process, Voltage and Temperature (PVT) variations) and under a wide range of activity levels or workload. In view of said spaces, we adopt the somewhat esoteric asynchronous-logic (async) vis-à-vis the conventional synchronous-logic (sync); more specifically, the Matched Delay (MD) and the Quasi-Delay-Insensitive (QDI). For an MD pipeline operating under a wide operation-space (alternating between active and idle), we propose a fine-grain power gating methodology (applicable to three different gating configurations) to reduce short-circuit and leakage wasted powers. By exploiting the 4-phase handshake protocol, the ensuing overhead of the proposed power gating is low, specifically one inverter (per pipeline stage) and <15% delay. For sake of robustness in view of the extreme/virtually intractable PVT in ultra low-power sub-threshold (sub-Vt) operation, where the circuit delay varies exponentially with PVT, we propose to adopt the QDI protocol. To quickly estimate to the first-order the delay variations (due to Vt, supply voltage (VDD) and temperature; thus the required delay safety margin) of digital circuits in sub-Vt, we propose and derive a set of simple yet insightful analytical equations. The derived equations are verified by simulations, and we show that they are accurate for first-order estimations (with an inconsequential worst-case error of <12%). We thereafter benchmark, by means of adder circuits, the sync (with delay safety margins estimated from the derived equations) against the async QDI (with self-completion detection), and ascertain that neither the sync nor the async QDI is particularly advantageous in all conditions. This exercise depicts the usefulness of the derived equations, particularly the insights provided thereto, and that delay variations are easily estimated from the nominal case. We propose a Sub-Vt Self-Adaptive VDD Scaling (SSAVS) system for a high variation-space and wide operation-space Wireless Sensor Network (WSN) with the objective of lowest possible power dissipation (in sub-Vt operation), yet high robustness and with minimal overheads. The effort to achieve the lowest possible power operation is by means of Dynamic-Voltage-Scaling (DVS) – self-adjusting VDD to the minimum voltage (within 50mV) for the prevailing conditions. High robustness is achieved by adopting the QDI protocol, and by the embodiment of our proposed ‘Pre-Charged-Static-Logic’ (PCSL) logic style; when compared against competing async logic styles appropriate for sub-Vt, the PCSL is most competitive in terms of energy/operation, delay and IC area. By exploiting the already existing request and acknowledge signals of the QDI protocol, the ensuing overhead of the SSAVS is very modest – a simple counter and a FIFO buffer. The filter bank embodied in the SSAVS is shown to be ultra low-power and highly robust. The proposed async SSAVS is benchmarked against its conventional sync Dynamic-Voltage-Frequency-Scaling (DVFS) counterpart for two scenarios. We show that no one system is particularly advantageous when the operating conditions are known. Further, when the sync DVFS system is designed for the worst-case condition, the proposed async DVS SSAVS is somewhat more competitive. To reduce the overheads of async QDI to improve its competitiveness, we propose a hardware-simplified version of QDI (herein coined ‘pseudo-QDI’) with an implicit timing for said SSAVS, and show analytically that said implicit timing is easily satisfied whilst ensuring robust operation. This robustness is verified by measurements on prototype ICs over high variation-space and wide operation-space. By means of the pseudo-QDI, the ensuing energy and area are significantly reduced by ~40% and ~1.34× respectively compared to the standardized QDI, with virtually no compromise to robustness.
URI: https://hdl.handle.net/10356/61794
DOI: 10.32657/10356/61794
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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