Process induced reliability of through silicon via
Date of Issue2014
School of Electrical and Electronic Engineering
Insatiable consumer demand for multifunctional and high performance integrated circuits and systems has necessitated three-dimensional (3D) integration with through silicon via (TSV) technology. 3D integration has provided a scaling path to reduce the wire length and power consumption. At the same time, it increases the input/output (I/O) density and communication bandwidth. In its simplest form, TSV is fabricated by high-aspect-ratio etching of silicon and filling with copper (Cu) by electroplating. Integration of TSV poses new challenges. Due to large CTE (coefficient of thermal expansion) mismatch between Si and Cu, large compressive stress is induced in the Si which causes mobility variation and mechanical deformation. TSV has strong electrical coupling with the doped Si substrate through the MOS structure. TSV parasitic capacitance has the most predominant impact on the circuit operation. It is therefore imperative to control the electrical parasitic and stress for successful TSV integration. Thus it is essential to measure and analyze the stress characteristics of the TSV structure. Among several potential techniques, the micro Raman spectroscopy appears to be particularly promising and is applied to measure the local stress distribution in Si near Cu TSVs. Copper filled TSV sample with diameter range from 4 to 10 μm with an interval of 1 μm were investigated. We also study the effects of different TSV liner materials on thermal stress relief. The two different liner materials are plasma enhanced tetraethylorthosilicate (PETEOS) SiO2 and carbon doped SiO2 Low-κ materials (SiCO). Confocal micro-Raman system LabRam HR by Horiba Scientific was used for the Raman measurements. Results from the experimental investigation were compared with the theoretical prediction (FEM performed by COMSOL®). The overall correlation between theory and experiment is reasonably good. It is found that the stress close to TSV decreasing rapidly while scaling down TSV from diameter of 10 μm to diameter of 4 μm due to the lower copper volume. By studying TSVs with different liner materials, we find it is also possible to control the stress level via the selection of a suitable liner material with a lower elastic modulus. The interesting findings can be attributed to the fact that the choice of a lower Young’s modulus and a porous dielectric liner material could effectively reduce the compressive near surface stress in Si.
DRNTU::Engineering::Electrical and electronic engineering::Microelectronics