Please use this identifier to cite or link to this item:
|Title:||Design of CMOS 60GHz Giga-bps communication system with CRLH T-line for high output power density and wide tuning range||Authors:||Fei, Wei||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2014||Source:||Fei, W. (2014). Design of CMOS 60GHz Giga-bps communication system with CRLH T-line for high output power density and wide tuning range. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Thanks to advanced scaling of CMOS technology, the operating speed and cut-off frequency of CMOS transistor steadily keeps growing more than 10 times and approaches to the millimeter-wave (mm-wave) region (60GHz – 140GHz @ 65nm node). Compared with III-V technologies, CMOS has the benefit of high integration and low cost, and therefore draws extensive research attention for system-on-chip implementation. Recently, substantial research activities about the wide frequency bands at 60 GHz and beyond have been accumulated to develop the next generation high-data-rate (>Giga-bps) wireless terminals in CMOS such as Wireless-HD, WiGiga for high-definition TV, projector and screen. Along with the new opportunities, there are also new challenges in design of CMOS mm-wave high-data-rate communication system. For example, one needs to achieve sufficient output power to cover the high path loss at mm-wave frequencies; and also to achieve wide tuning range to cover the large spectrum for high-data-rate communication. However, these features are constraint by advanced CMOS technologies at mm-wave frequencies with low supply and breakdown voltages and large PVT variation. For example, one fundamental block for mm-wave IC design, transmission line (T-line), has fundamental limitations on circuit performance due to the traditional right-handed (RH) topology. This work provides design analysis as well as on-chip demonstration to resolve the aforementioned design challenges for mm-wave integrated circuit (IC) design in CMOS technology. A transformation of mm-wave IC design with the use of metamaterial is mainly explored in this work. Metamaterial is not a new type of material, but a periodic unit-cell structure that can be implemented on-chip in common CMOS technologies. The unique feature of the metamaterial is to provide nonlinear negative phase shift that can be realized in compact area, which can be utilized for high efficiency output power combining as well as wide frequency tuning. Based on this observation, we have explored the application of on-chip metamaterial for two critical blocks in 60GHz high-data-rate communication system: power amplifier (PA) and voltage controlled oscillator (VCO). For PA design, the target is to improve the output power density and bandwidth performance. With the use of one type of metamaterial transmission line (T-line), composite-right-left-handed (CRLH) T-line, a new 2D distributed in-phase power combining network is developed to provide distributed amplification and power combining within compact area simultaneously. As such, one can achieve high output power, high output power density and wide-band performance for CMOS 60GHz PA and transmitter, which are realized as follows: • One 60GHz PA prototype with single-ended 2×2 power combining was first fabricated in UMC CMOS 65nm technology. Measured results show 8.3dB gain, 7.1% PAE, and 9.7dBm P1dB with 16GHz bandwidth (44 to 60GHz) and area of 0.39mm2. This work was further improved to have a differential topology with compact transformer matching, and was implemented in GF CMOS 65nm technology. • Two 60GHz PA prototypes with differential 2×4 and 4×4 power combining were demonstrated. The measured results show state-of-art performance, with 13.2 dB gain, 8.7% PAE, 20GHz bandwidth (53 to 73GHz) and 13dBm output power with 74.5mw/mm2 output power density for the 2×4 PA; and 17.5dB gain, peak PAE of 11.3%, 8.8GHz bandwidth (54 to 62.8GHz), and 16.6dBm output power with 95.2mw/mm2 output power density for the 4×4 PA. • Based on the above chip realization and verification, one 60GHz direct-conversion transmitter with the proposed 2x4 power combining was implemented in GF CMOS 65nm technology with functionality verified by post-layout simulation at system level. For VCO design, the target is to improve frequency tuning range (FTR) with maintained low phase noise performance. One inductive tuning method is first proposed based on configuration of current return paths in the secondary coil of a transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60GHz within compact area by only one transformer. Furthermore, a distributed CRLH T-line based VCO is designed in a Mobius-ring rotary-traveling-wave (RTW) topology to further improve FTR. RTW VCO is commonly adopted due to its advantages such as easy placement of cross-coupled transistors, good matching of differential blocks and compact area. Based on inductive tuning, a tunable CRLH T-line is proposed. Because of the nonlinear dependence of phase-change with frequency, wide FTR mechanism can be achieved for RTW VCO in millimeter-wave region. The CRLH T-line is implemented in RTW-VCO with inductor-loaded transformer to realize sub-band selection over a wide FTR. Each sub-band is further covered by a varactor for fine-tuning. As such, one can achieve wide FTR with low phase noise in each sub-band for CMOS 60GHz VCO and PLL, which are realized as follows: • Two 60GHz VCOs were demonstrated in 65nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3GHz with phase noise variation of ±8.2dB (-90.2 to -106.7dBc/Hz at 10MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of ±2.5dB (-105.9 to -110.8dBc/Hz at 10MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz. • The third RTW VCO chip was fabricated in GF 65nm RF-CMOS technology with area of 0.08mm2. The measured results show a current consumption of 14mA under supply voltage of 1V, a tuning range of 29.5% with center frequency at 89.3GHz, and a phase noise from -100.1dBc/Hz to -98.7dBc/Hz with 10MHz offset. A state-of-art figure-of-merit FOMT of -177.78dBc/Hz is demonstrated. Based on the above chip realization and verification, one 60GHz PLL with the proposed symmetric inductive tuned VCO was implemented in GF CMOS 65nm technology with functionality verified by post-layout simulation at system level.||URI:||http://hdl.handle.net/10356/61825||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.