Network design and characterization for ZedWulf

Abstract

In recent times, we see an increasing amount of research interest in exploring the usage of ARM architectures in High Performance Computing (HPC). While pure ARM chips have historically been lacking the performance edge over x86, ARM-FPGA hybrid designs such as the Zynq SoC can be the potential catalysts. In this project, we build a cluster composed of 32 such Zynq-based devices (Zedboards) to accelerate sparse-graph oriented problems, which are typically memory-bottlenecked on traditional x86 systems. We employ Message Passing Interface (MPI) to design an optimized scatter technique for supporting sparse-graph oriented irregular memory accesses across the cluster. We then formulate a performance model with a coefficient of determination more than 90% for understanding runtime scaling trends for our novel scatter-gather routine. We also run micro-benchmarks to understand Memory System, AXI – Accelerator Coherency Port (ACP) and Network characteristics of the Zedboard in the presence of Xillinux OS