Design of a variable rate low power SAR ADC with bypass window for biomedical application
Date of Issue2014
School of Electrical and Electronic Engineering
Centre for Integrated Circuits and Systems
In recent years, there is an increasing demand for portable, wearable or implantable biomedical devices. These devices generally require extremely long battery life-time which in turn demands extremely low-power band-pass filters, low-noise amplifiers and low-power ADC. SAR ADC is typically adopted in these devices because of its higher power efficiency compared to other ADC architectures (e.g., flash ADC, pipeline ADC). Nevertheless, a big proportion of energy is still consumed by the conventional SAR ADC. Hence, extensive research is still required to further lower the power consumption. Meanwhile, many biomedical signals vary slightly within a small range for a large portion of time. Incorporating this signal characteristic into the design, a bypass window technique that can increase the power efficiency of the SAR ADC in biomedical signal acquisition is proposed here. This technique is based on the idea that when the input signal is within a predefined range, several conversion steps for the first few significant bits are bypassed, i.e., fewer switching instances happen in the capacitive DAC and hence less power is consumed during the switching sequence. Besides, the design has a 2-stage low-power dynamic comparator and a TSPC DFF constructed phase generator, which helps to lower the overall power consumption further for our SAR ADC. In the current project, the SAR ADC is designed and implemented in GLOBALFOUNDARIES 40nm CMOS process. The simulation results show that with sampling frequency from 0 to 2MHZ, this ADC can achieve a SNDR of 61.55dB and ENOB of 9.93bits. It can reduce 74% of the power dissipation if the bypass window function is triggered.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits