Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/62234
Title: A low-power accelerometer IC with high sensitivity
Authors: Wang, Yan Mei
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2015
Source: Wang, Y. M. (2015). A low-power accelerometer IC with high sensitivity. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: The objective of this project is to design a low-power, low-noise, highly-sensitive accelerometer ASIC interface using standard CMOS technology. The capacitive acceleration sensor is based on Micro-Electro-Mechanical Systems (MEMS) technology. For the targeted security applications, the bulk-micromachined accelerometer which has been developed by Temasek Laboratory@NTU, is employed as the sensing element to couple with the abovementioned ASIC readout circuit. The auto-zero time-multiplexed differential technique is able to tolerate a number of circuit non-idealities. These include operational amplifier (op-amp) offset, offset thermal drift and switch errors of switched-capacitor (SC) circuits. The unique single-ended circuit architecture avoids the stringent requirement for component matching and eliminates the common-mode problem in conventional fully differential interface circuitry. Ultimately, it improves S/N ratio and cancels the common-mode errors in the sensing system with low power consumption. For the implementation of the ASIC design to the intended accelerometer application, it involves several circuit building blocks. They are readout circuit, oscillator, differential-to-single-ended SC gain amplifier stage, passive RC filter and low-offset low-noise op-amp buffer. A novel Auto-Zero Time-multiplexed Capacitance-to-Voltage Converter (AZTMD-CVC) is proposed for the readout circuit in this project. The circuit architecture achieves differential output performance whilst using only single-ended CVC topology. This approach eliminates the use of bulky full Wheatstone bridge sensing element in the MEMS sensor as required in conventional fully differential sensor interface architecture, with additional benefit in reducing the fabrication cost of the MEMS sensor and readout circuit, as well as the power consumption. Besides, a low-power design strategy, pertaining to power versus noise in the readout circuit, is proposed. It permits the design to attain low noise without using excessive power consumption. This offers the optimal power-noise product in a form of figure-of-merit (FOM) on the AZTMD-CVC. Two new oscillator circuits have been presented in this work. Both the oscillator designs offer clock signals with good temperature and supply variation immunity. The first oscillator design is a compact low-power CMOS ring oscillator with temperature and supply compensation whereas the second oscillator design deals with the relaxation oscillator using the tracking current comparator. The second design is adopted in this AZTMD-CVC circuit together with the silicon implementation for prototype testing. The key feature of the second oscillator is that of the temperature compensation without resorting to any external resistor component. The tracking current comparator based oscillator provides a 172 kHz clock for the interface circuit. This clock signal displays a 0.17% variation within the supply range from ±1.6V to ±2V whereas the mean temperature compensated coefficient for 5 samples of this oscillator frequency is around 0.018%/°C with a temperature range of -40 to 90°C. The power consumption of this oscillator circuit is only 4.2uA (21uW), demonstrating low-power consumption feature. The accelerometer ASIC has been designed and implemented using the AMS 0.35µm CMOS 3.3/5V process technology. This accelerometer interface IC features both the offset and gain trimming which enable the IC to operate correctly even under the process variation of the fabricated MEMS capacitance sensor. The prototype testing results have shown that the accelerometer readout system achieves a sensitivity of 1.95V/g. The system achieves a low noise level of -100 dBm/Hz, which corresponds to an equivalent acceleration noise of 1.16 µg/√Hz. The total power consumption including the clock generator is only 1.2 mW with 2.5V dual supplies. The measured in-run bias stability under 0g acceleration is 7.5 µg over around 3 hours’ time. This is comparable with other reported highly-sensitive accelerometers. This measurement results have validated that the proposed design can meet low-power low-noise objectives with very high sensitivity. It outperforms the reported state-of-art works in performance comparison.
URI: https://hdl.handle.net/10356/62234
DOI: 10.32657/10356/62234
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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