dc.contributor.authorOng, Ran Xing
dc.date.accessioned2015-04-14T06:34:28Z
dc.date.accessioned2017-07-23T08:37:56Z
dc.date.available2015-04-14T06:34:28Z
dc.date.available2017-07-23T08:37:56Z
dc.date.copyright2015en_US
dc.date.issued2015
dc.identifier.citationOng, R. X. (2015). Investigation of interconnect layout on CU/Low-K TDDB reliability. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/62521
dc.description.abstractTraditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on TDDB lifetime is examined. First, the effect of area was examined. It was found that lifetime data gathered from small head-to-head geometries commonly seen in actual circuits cannot be extrapolated to large are conventional comb structures. Secondly, the effect of having adjacent metal lines in close proximity was studied. The interaction of the electric field between adjacent electrodes was found to lead to a decrease in the TDDB lifetime. Finally, the effect of electromigration (EM) in the metal line was investigated. Compressive stress induced by EM deforms the metal line, leading to reduction of the dielectric spacing, causing the TDDB to be shortened.en_US
dc.format.extent143 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Materials::Microelectronics and semiconductor materialsen_US
dc.titleInvestigation of interconnect layout on CU/Low-K TDDB reliabilityen_US
dc.typeThesis
dc.contributor.schoolSchool of Materials Science and Engineeringen_US
dc.contributor.supervisorGan Chee Lipen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (MSE)en_US


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