Please use this identifier to cite or link to this item:
|Title:||Investigation of interconnect layout on CU/Low-K TDDB reliability||Authors:||Ong, Ran Xing||Keywords:||DRNTU::Engineering::Materials::Microelectronics and semiconductor materials||Issue Date:||2015||Source:||Ong, R. X. (2015). Investigation of interconnect layout on CU/Low-K TDDB reliability. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on TDDB lifetime is examined. First, the effect of area was examined. It was found that lifetime data gathered from small head-to-head geometries commonly seen in actual circuits cannot be extrapolated to large are conventional comb structures. Secondly, the effect of having adjacent metal lines in close proximity was studied. The interaction of the electric field between adjacent electrodes was found to lead to a decrease in the TDDB lifetime. Finally, the effect of electromigration (EM) in the metal line was investigated. Compressive stress induced by EM deforms the metal line, leading to reduction of the dielectric spacing, causing the TDDB to be shortened.||URI:||http://hdl.handle.net/10356/62521||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||MSE Theses|
Files in This Item:
|INVESTIGATION OF INTERCONNECT LAYOUT ON CU LOW-K TDDB RELIABILITY.pdf||5.4 MB||Adobe PDF|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.