Sensor signal conditioning circuit design for multi-electrode intra-cortical recording
Date of Issue2014
School of Electrical and Electronic Engineering
Brain-Machine Interfaces (BMIs) have been developed in the past few decades to establish a bridge between brain and external electronics and computing devices. Driven by an increasing demand in health care industry and the rapid development of complementary metal oxide semiconductor (CMOS) and micro-electro-mechanical systems (MEMS) technology, significant progress has been made in the BMIs that interpret the electrical signals of the brain in order to study the brain functions or to control an actuator. The trend is to develop cortex-implantable miniature devices integrating entire system that are bio-compatible and are able to operate chronically and autonomously. This raises significant challenge to various aspects of systems and circuits design of the BMIs due to limited resource and budget. One promising version of these systems is sensing neural extracellular action potentials with an array of up to 100 or more miniature probes implanted into the cortex. To guarantee the quality of the neural signal recorded by these high impedance electrodes, customized integrated circuits (IC) are developed with multiple amplifiers on the same die, achieving on-site signal recording. Since power consumption is one of the key limiting factors of the implanted system, significant effort has been dedicated to reduce the power consumption of the front-end analog and mixed-signal circuits. However, high channel count also yields high data transmission rate, leading to considerable power consumption in wireless transmission circuits. Methods of on-chip data compression are therefore highly desirable in the implanted system. In this thesis, circuits are presented for sensing and processing the neural signals robustly while dissipating minimal power and reducing data rate for enhancing scalability of the designs. The first contribution is the design of a novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/fn characteristics of the neural signals is proposed to reduce the dynamic range in the front-end circuits. The amplified output is ‘folded’ into a predefined range of voltage by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm is applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range at final output. It, therefore, reduces the transmission data rate of the recording chip. Both of these features allow power and area saving at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, less harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a MATLAB-based behaviour model for signal folding amplifier introduced to provide estimates for reconstruction error. Measurement results from two designs in two different CMOS processes are presented to prove the generality of the proposed scheme in neural recording applications. In-vivo testing results on anaesthetized rat are also conducted to show the capability of the proposed neural amplifier to simultaneously record local filed potential and spike. Another emerging trend of BMIs in recent years is to implement neural stimulator with neural recording circuits to build a brain- machine-brain closed loop in the implanted system. These closed-loop BMIs find vast applications in therapies of neurological disorders, neural prosthesis and neuro-scientific research, where certain action potential in the brain tissue are observed as a response to the neural stimulation delivered. One challenge of building the closed-loop BMIs is to record as much of the action potential waveform as possible in the presence of large artifacts introduced by the neural stimulation. These artifacts, much larger than the action potential, usually cause the saturation of the high-gain neural recording amplifier and create a long blind period of tens of milliseconds during and right after the stimulation, in which action potential cannot be properly recorded. Applying the proposed signal folding and reconstruction scheme mentioned above, a proof-of-concept IC is presented in this thesis, targeting simultaneous neural stimulation and recording. The testing results shows that the signal folding scheme creates a feedback loop that prevents the amplifier from saturation by resetting the amplifier even with artifacts at the input, leading to a reduced recovery time from the interference of the stimulation artifacts. This is the second contribution in this thesis. Signal processing circuits can also be integrated with microelectrode array (MEA) to enable real-time on-chip processing and reduce the data transmission rate as well as the power consumption. In the BMIs used in neural prosthesis, one key component is the motor intention decoder that extracts the subjects’ intention of moving from the neural signals recorded in the motor cortex of the brain. A hardware-friendly motor intention decoding algorithm based on the Extreme Machine Learning (ELM) and its mixed-signal CMOS implementation is presented in this thesis as the final contribution. ELM is a single hidden-layer neural network, in which input weights are randomly assigned and remain unchanged in training. Only output weights are trained in a one-time manner, leading to a very fast training progress and reduced computing efforts. This neural network is realized in a mixed-signal architecture, in which random weights are implemented by exploiting transistor random mismatch in the CMOS process, while output weights are implemented in digital domain for robustness and programmability. The results of decoding neural signal data (recorded in previously conducted animal experiments) with the proposed algorithm are shown and analyzed. In conclusion, BMIs with multiple electrodes implanted in the cortex have experienced fast development in recent years. Next generation BMI will possibly integrate up to one thousand micro-electrodes with circuit components including neural recording, signal processing as well as sensory feedback, leading to a better performance and possibly more applications. In the BMI for neural prosthesis, for instance, better control accuracy and robustness can be obtained with more intra-cortical recording and feedback. Types of prosthesis can also be extended from, for instance, upper limb to bipedal. In this great interdisciplinary endeavor, power consumption and robustness of the electronics system will always be a limiting factor to the practical use of the devices. In this thesis, some problems of the front-end signal amplifying circuit of intra-cortical BMIs have been addressed and low-power solutions have been proposed. Architectural solutions to enhance scalability and reducing transmission data rate by integrating a movement classifier on-chip is also shown for the first time.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits