Please use this identifier to cite or link to this item:
Title: FPGA-based investigation of coding and detection for non-volatile memories
Authors: Lim, Melvin Heng Li
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2015
Source: Lim, M. H. L. (2015). FPGA-based investigation of coding and detection for non-volatile memories. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: The low-density parity-check (LDPC) codes are by far the best error-correction codes discovered till date, providing exceptional performances that verge on the theoretical boundary, otherwise known as the Shannon limit. Yet, in the process of manipulating its enticing features, modern LDPC applications, explicitly the non-volatile memories (NVM), are more often than not encumbered by its very decoding mechanism of recursive nature, which fuels the capacity-approaching performances of the LDPC codes. This thesis therefore demonstrates numerous propositions pertaining to cost-effective high-throughput implementation of the LDPC decoders on field-programmable gate-array (FPGA) hardware, alongside ingenious techniques to compensate for certain performance loopholes in LDPC decoding. Moreover, the possibility and potential of amalgamating two or more of the proposed works have been accomplished and substantiated in this thesis, rendering a concerted effect of high-throughput decoding and low-complexity realization while retaining outstanding decoding performances.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
  Restricted Access
2.3 MBAdobe PDFView/Open

Page view(s)

Updated on Nov 25, 2020


Updated on Nov 25, 2020

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.