Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/63517
Title: Power-stage design for switched- mode DC-DC converter
Authors: Lim, Yong Siah
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2015
Abstract: This project pertains to the design of power transistors for a high switching-frequency DC-DC converter. We investigate the optimum tapering factor to design the buffer for the power transistors. Simulation results of the power transistors with the buffer designed with the optimum tapering factor show a 91% power-efficiency improvement as compared to that with the conventional tapering factor. We investigate the optimum sizing method for the power transistors. Further, we investigate the low-swing method for the buffer design. We apply the optimum tapering factor, the optimum sizing method, and the low-swing method to our buffer and power transistor design. Simulation results at 5 MHz, 1.65 V output voltage, and 280mA output current show that our design achieves a 3% power-efficiency improvement as compared to that of a conventional full-swing method (with the same optimum tapering factor and the optimum sizing method). We reduce the in-rush current by using the low-swing method and implementing a dead-time. Simulation results of the buffer and the power transistors with the low-swing method and the dead time (together with the optimum tapering factor and the optimum sizing method) show that the in-rush current reduced by 3A as compared to the design without the low-swing method and the dead-time.
URI: http://hdl.handle.net/10356/63517
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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