Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/63778
Title: Asynchronous QDI library cell layout development and characterization
Authors: Choy, Joel Guo Wen
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2015
Abstract: This report presents the Design of Asynchronous Quasi-Delay-Insensitive (QDI) Library Cell Layout Development and Characterization. Asynchronous clock-less circuits are used in digital system that serves as an alternative for synchronous circuits. In asynchronous circuits, it employs hand-shaking protocol that replaces the need for a timing circuit. The advantageous of a QDI realization approach is that it is highly robust towards process, voltage and temperature (PVT) variation as any timing assumptions are eliminated. Because of the lack of Electronic Design Automation (EDA) tools to synthesis QDI cell libraries, there is a need for these cell layouts to be hand-drafted. With these hand-drafted library cells created, IC designers are able to utilize the cells for future work where the designs are larger and more complex. The technology used for this design is CMOS 0.65μm, using the Globalfoundries technology. This report also presents the process flow of an IC design and the use of EDA tools such as Cadence Virtuoso Schematic Capture and Layout Editor. While designing critical checks to ensure the functionality of the layout was done using Calibre Layout Versus Schematic (LVS) and to adhere to the foundry’s process and to reduce fabrication faults, Calibre Design Rule Check (DRC). As the designing stages are always in ideal conditions, parasitic capacitance and resistance has to be extracted. This was done using Calibre Parasitic Extraction (PEX). With the extraction of parasitic capacitance and resistance, rise and fall delay time can be simulated to mimic real-world conditions. After completing the library cell designs for 54 cells, simulated results from pre and post layout are compared to ensure that the functionality is similar. Next, with the already available synchronous combinational logic cells, they are characterized using Synopsys SiliconSmart. An 8051 microcontroller was synthesized using Synopsys Design Vision and the floor planning together with the placing and routing of the microcontroller was done using Cadence Encounter. To date, different transistor widths has been designed, verified and simulated.
URI: http://hdl.handle.net/10356/63778
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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