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|Title:||High-Speed ADC||Authors:||Lu, Qian Qian||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2015||Abstract:||As an interface of analog and digital domain, high-speed ADC with moderate-to-high resolution and low power consumption is expected in many applications. In this final year project, a fully differential SAR ADC is designed and implemented in Global Foundries 65nm CMOS process. It consists of a dynamic comparator with offset calibration, binary-weighted capacitive array with attenuation capacitor and SAR control logic circuit. The simulation results show that with sampling frequency 166MHz, this ADC can achieve a SNDR of 47.27dB and ENOB of 7.56bits at 82.1MHz input frequency and SNDR of 49.50dB and ENOB of 7.93bits at 3.9MHz input frequency. The peak-to-peak voltage of differential input signal is 0.6V with common mode voltage 900mV. The ADC consumes 2.3mW at 1.2V supply voltage. It achieves an FOM of 54.75fJ/conversion-step.||URI:||http://hdl.handle.net/10356/63831||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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