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Title: | Thermal management of integrated electronics | Authors: | Koh, Sheilina Yu Fang | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Microelectronics | Issue Date: | 2015 | Abstract: | With technology advancing exponentially, sizes of these electronic devices are decreasing as well. As the sizes decreases, the area for heat dissipation will be smaller. This will in turn lead to a rise in temperature which the integrated circuit (IC) may not be able to withstand. This may cause the performance of the IC to be unreliable. The cooling method that is chosen must be able to dissipate heat fluxes that are above 100W/cm2 with the operating temperature not exceeding 80°C. Thus, it is essential to remove heat efficiently that is dissipated which may potentially cause damage to the IC. In order to cool the IC efficiently, various technologies are explored. The technologies are liquid cooling using microchannels, use of heat pipes, thermoelectric cooling, metal vapor chamber, etc. The technology that is used in this project is metal vapor chamber. This technology is chosen as it has been studied extensively and possesses superior heat dissipation capabilities than the others. A vapor chamber consists of evaporator with a heat source, condenser with a heat sink and an adiabatic section. The author has worked with the research team at Singapore-MIT Alliance for Research and Technology with regard to this problem. Through this report, the author will present the thermal management technique chosen and discuss the results obtained with the use of micropillar arrays. Different geometries (e.g. micropillar height, pitch, diameter and array length) fabricated on wick length of 1.0 cm were investigated. The samples were tested in sealed vapor chamber environment. This was done in the analytic model developed by the team at SMART. As the setup has its limitation, the author could capture the data during the experiment qualitatively. In order for efficient heat removal, higher pillar diameter/ pitch ratio, higher aspect ratio and low wick array lengths are required. | URI: | http://hdl.handle.net/10356/63871 | Schools: | School of Electrical and Electronic Engineering | Research Centres: | Singapore-MIT Alliance Programme | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
Files in This Item:
File | Description | Size | Format | |
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FYP_Report_SHEILINA_FINAL.pdf Restricted Access | Summary of Final Year Project (experiment data) | 1.51 MB | Adobe PDF | View/Open |
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