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|Title:||PGA design for RFIC||Authors:||Wang, Guanzhong||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2015||Abstract:||Programmable gain amplifiers (PGA) are widely used across different applications nowadays such as hard disk drives and wireless communication systems. It is implemented into a system to provide output signals in a constant range to be used for analog-to-digital converter (ADC) despite large variations of input signals. Programmable gain amplifiers are desired to be designed to have lower power consumption, higher gain linearity and wider bandwidth for different usages. In this project, previous works on PGA are reviewed, mainly common-mode feed-forward pseudo differential pair topology and binary-weighted switching technique. A PGA based on common-mode feed-forward pseudo differential pair topology is improved in GF 65nm process. Simulations have been done on the proposed PGA in Cadence simulation environment. According to the simulation results, the -3dB bandwidth of the PGA is around 1.25GHz, and the gain error is less than ±2.1dB, while the power consumption of the circuit is around 2.25mW. The input-referred 1dB compression point values are in the range of -19.62 to -0.71dBm and input-referred third order intercept point values are between -10.01 to 18.53dBm.||URI:||http://hdl.handle.net/10356/64167||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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