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|Title:||A three-level inverter for electrical drives||Authors:||Teng, Jian Yao||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2015||Abstract:||An electrical drive is an electromechanical system that uses the electric motor as its prime mover to impart motion to various machines and mechanisms. The Permanent Magnet Synchronous Motor (PMSM) is used in many applications that require fast dynamic torque response. This is achieved through the use of Direct Torque Control (DTC) technique. In the market today, classical DTC, which uses a two-level voltage source three-phase inverter, is largely adopted. However, it has several drawbacks such as larger torque ripples and also higher harmonic content in the output voltage. In this project, a novel DTC with three-level multilevel inverter is proposed. The use of three-level inverter has allowed more voltage vectors to be available for selection (27 compared to 8 in classical two-level inverter) in more precise control of the torque and flux. This has successfully reduced the magnitude of the torque ripples by 32%, enhancing the performance of the drive for more demanding motion control and at the same time, lower the acoustic noise and improves the stability of the system. The optimisation of voltage vectors to cater for more levels of torque and flux demand also helps to save energy, reduce wear and tear, and increase the efficiency of the system. The three-level NPC inverter is also capable of reducing the harmonic distortion of the output voltage by 49% from 91.43% in the two-level inverter to 42.43% in three-level. A high level of harmonics degrade the cable insulation and leads to overheating of the motor, which reduces its shelf-life. As the motor is often the most expensive piece of equipment in the drive, this helps to save on the maintenance and replacement cost. Other original contributions include the use of 2-D and 3-D matrices to condense the exhaustive amount of if-else statements in the DTC algorithm to make it more concise and with faster run-time. Also, the implementation of the analog dead time generator instead of the typical digital FPGA to provide the dead time for the switching signals is unique and eliminates any processing and sampling delay, or limited resolution. No level-shifters (required for FPGA) are required, which cuts down on wire connections and also the risk of loose connections, to make the system more compact and sturdy.||URI:||http://hdl.handle.net/10356/64218||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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