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https://hdl.handle.net/10356/64229
Title: | Digital controller design of class-D amplifier | Authors: | Wang, Zhaotian | Keywords: | DRNTU::Engineering::Electrical and electronic engineering | Issue Date: | 2015 | Abstract: | The digital Class-D amplifiers are more and more prevalent in audio applications.A digital Class-D amp has several advantages: high power conversion efficiency, low heat dissipation and small scale. The biggest advantage of digital control is that all signals from the processor to the controlled object are in digital, without further digital-analog conversion process. The anti-jamming capability against noise is also greatly enhanced.In general, a digital Class-D amplifier includes a pulse width modulator and an output stage. The aim of the project is to design the digital controller and write the corresponding Verilog code. To be more specific, the project has two main parts. The first part of this project concentrated on the design of the linear interpolation sampling process (LI). The first part also showed a parallel divider design in the LI sampling process. The second part focused on the PWM generator. Besides, the corresponding Verilog code has been written and simulated in Modelsim SE. | URI: | http://hdl.handle.net/10356/64229 | Schools: | School of Electrical and Electronic Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
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FYP Report.doc.pdf Restricted Access | 908.48 kB | Adobe PDF | View/Open |
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