Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/64229
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dc.contributor.authorWang, Zhaotian
dc.date.accessioned2015-05-25T06:56:00Z
dc.date.available2015-05-25T06:56:00Z
dc.date.copyright2015en_US
dc.date.issued2015
dc.identifier.urihttp://hdl.handle.net/10356/64229
dc.description.abstractThe digital Class-D amplifiers are more and more prevalent in audio applications.A digital Class-D amp has several advantages: high power conversion efficiency, low heat dissipation and small scale. The biggest advantage of digital control is that all signals from the processor to the controlled object are in digital, without further digital-analog conversion process. The anti-jamming capability against noise is also greatly enhanced.In general, a digital Class-D amplifier includes a pulse width modulator and an output stage. The aim of the project is to design the digital controller and write the corresponding Verilog code. To be more specific, the project has two main parts. The first part of this project concentrated on the design of the linear interpolation sampling process (LI). The first part also showed a parallel divider design in the LI sampling process. The second part focused on the PWM generator. Besides, the corresponding Verilog code has been written and simulated in Modelsim SE.en_US
dc.format.extent55 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleDigital controller design of class-D amplifieren_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorYu Jun
dc.contributor.supervisorGoh Wang Lingen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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