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|Title:||Investigation and implementation of multilevel power converters for low/medium/high power applications||Authors:||Ooi, Gabriel Heo Peng||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2015||Source:||Ooi, G. H. P. (2015). Investigation and implementation of multilevel power converters for low/medium/high power applications. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The presented research work explores and proposes an efficient multilevel converter for single dc bus configuration without any isolated dc sources connected in the dc-link. The experimental prototype in a three-phase/three-level rectifier topology is focused on four functionalities of the unity power factor controller: (a) dc-link voltage balancing, (b) switching frequency range to achieve low THD current, (c) fault tolerance capability for two-phase operation, and (d) dynamic response of a feed-forward current control. The dc-link voltage balancing method for the three-phase/three-level and three-phase/five-level inverter topologies for neutral-point-clamped (NPC) inverter and flying capacitor (FC) inverter are also investigated. According to the experimental results, balanced capacitor voltage in the dc-link of a three-phase/three-level NPC inverter are achieved by using the dc offset modulation. However, three-phase/five-level/multilevel diode-clamped inverter (5L-MDCI) topologies require additional active balancing circuit in order to achieve stable and balanced capacitor voltages in the dc-link. The RC filter voltage balancing approach is well suited for flying capacitor inverter topology with more than three-levels based on PS-PWM technique. The optimum reduction on the component count in five-level converters (rectifier and inverter) is proposed. Both five-level rectifier and inverter topologies are developed based on the multiple-pole concept. This approach reduces the number of power semiconductor devices with distributed voltage sources in a single dc bus configuration. By observing the switching operation of a level-shifted pulse width modulation (LS-PWM) in multiple-pole multilevel converters, zero current switching is achieved in the inner cell switch naturally. The multiple-pole multilevel rectifier with reduced number of physical measurements sensors is achieved by implementing an observer control technique. Even when single phase fault is experienced, continuous operation is achieved for the five-level multiple-pole unity power factor rectifier topology using the proposed sensorless grid voltage and load current method. A high control bandwidth for two-phase operation is possible under severe unbalanced three-phase grid condition. The two-phase operation in a three-phase multiple-pole multilevel UPF rectifier is carried out with an in-phase current control technique based on balanced power condition in a three-phase three-level rectifier. A 1 kHz LS-PWM is developed for five-level rectifier topologies in order to take advantage of its simplicity and well regulated switching profile. In order to limit the switching loss to minimum a shorter conduction period control is proposed for a three-phase/five-level/six-switch multiple-pole multilevel UPF rectifier configuration. The hybrid-switching scheme based on LS-PWM/PS-PWM and shorter conduction period minimizes the switching losses incurred by inner cell switches THD of the input grid current under light load conditions. Overall, the hardware prototypes of proposed converters have been totally realized and experimental results of Chapters 3 to 12 (except Chapter 11) are verify all analytical results and guarantee an optimum performance converter.||URI:||https://hdl.handle.net/10356/64275||DOI:||10.32657/10356/64275||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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Updated on Jun 12, 2021
Updated on Jun 12, 2021
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